A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.