Invention Grant
- Patent Title: Memory with read cycle write back
- Patent Title (中): 内存读取循环回写
-
Application No.: US12474078Application Date: 2009-05-28
-
Publication No.: US08009489B2Publication Date: 2011-08-30
- Inventor: Shayan Zhang , Jack M. Higman , Prashant U. Kenkare , Pelley H. Perry , Andrew C. Russell
- Applicant: Shayan Zhang , Jack M. Higman , Prashant U. Kenkare , Pelley H. Perry , Andrew C. Russell
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent David G. Dolezal; James L. Clingan, Jr.
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/02

Abstract:
A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.
Public/Granted literature
- US20100302837A1 MEMORY WITH READ CYCLE WRITE BACK Public/Granted day:2010-12-02
Information query