A semiconductor memory device using a full-VDD bit line precharge scheme by using a bit line sense amplifier includes a precharge unit precharging a bit line and a complementary bit line from a power voltage to a voltage that is less than the power voltage by a predetermined voltage, and the bit line sense amplifier including first and second transistors serially connected between the bit line and the complementary bit line to be cross-coupled to each other, wherein a gate of the first transistor is connected to the complementary bit line and a gate of the second transistor is connected to the bit line. The precharge unit precharges, in response to a first precharge signal, the bit line and the complementary bit line to a voltage that is less than the power voltage by a threshold voltage of the first or second transistor, and precharges, in response to a second precharge signal, the bit line and the complementary bit line from the power voltage to a voltage that is less than the power voltage by half of a threshold voltage of the first or second transistor.