Invention Grant
- Patent Title: Four-gate transistor analog multiplier circuit
- Patent Title (中): 四门晶体管模拟乘法电路
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Application No.: US11804893Application Date: 2007-05-21
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Publication No.: US08010591B2Publication Date: 2011-08-30
- Inventor: Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
- Applicant: Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
- Applicant Address: US CA Pasadena
- Assignee: California Institute of Technology
- Current Assignee: California Institute of Technology
- Current Assignee Address: US CA Pasadena
- Agency: Milstein Zhang & Wu LLC
- Agent Joseph B. Milstein
- Main IPC: G06E3/00
- IPC: G06E3/00

Abstract:
A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
Public/Granted literature
- US20080001658A1 Four-gate transistor analog multiplier circuit Public/Granted day:2008-01-03
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