Invention Grant
- Patent Title: Automated method for buffering in a VLSI design
- Patent Title (中): 用于在VLSI设计中缓冲的自动化方法
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Application No.: US12032762Application Date: 2008-02-18
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Publication No.: US08010922B2Publication Date: 2011-08-30
- Inventor: Frank Malgioglio , Adam R. Jatkowski , Brian A. Lasseter , Joseph J. Palumbo
- Applicant: Frank Malgioglio , Adam R. Jatkowski , Brian A. Lasseter , Joseph J. Palumbo
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent William A. Kinnaman, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.
Public/Granted literature
- US20090210842A1 Automated Method for Buffering in a VLSI Design Public/Granted day:2009-08-20
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