Invention Grant
- Patent Title: Method and system for placement of electric circuit components in integrated circuit design
- Patent Title (中): 集成电路设计中电路元件放置的方法和系统
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Application No.: US12121397Application Date: 2008-05-15
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Publication No.: US08010925B2Publication Date: 2011-08-30
- Inventor: Markus Buehler , Juergen Koehl
- Applicant: Markus Buehler , Juergen Koehl
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent John E. Campbell; Lynn L. Augspurger
- Priority: EP07109419 20070601
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.
Public/Granted literature
- US20080301612A1 Method and System for Placement of Electric Circuit Components in Integrated Circuit Design Public/Granted day:2008-12-04
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