Invention Grant
US08010932B2 Structure for automated transistor tuning in an integrated circuit design
有权
用于集成电路设计中自动晶体管调谐的结构
- Patent Title: Structure for automated transistor tuning in an integrated circuit design
- Patent Title (中): 用于集成电路设计中自动晶体管调谐的结构
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Application No.: US12130476Application Date: 2008-05-30
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Publication No.: US08010932B2Publication Date: 2011-08-30
- Inventor: Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
- Applicant: Christopher M. Durham , Peter J. Klim , Robert N. L. Krentler
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Dillon & Yudell LLP
- Main IPC: G06F9/455
- IPC: G06F9/455
Abstract:
A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.
Public/Granted literature
- US20080229260A1 STRUCTURE FOR AUTOMATED TRANSISTOR TUNING IN AN INTEGRATED CIRCUIT DESIGN Public/Granted day:2008-09-18
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