The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.