Invention Grant
US08011090B2 Method for forming and planarizing adjacent regions of an integrated circuit
有权
用于形成和平面化集成电路的相邻区域的方法
- Patent Title: Method for forming and planarizing adjacent regions of an integrated circuit
- Patent Title (中): 用于形成和平面化集成电路的相邻区域的方法
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Application No.: US12123021Application Date: 2008-05-19
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Publication No.: US08011090B2Publication Date: 2011-09-06
- Inventor: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- Applicant: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H05K3/02
- IPC: H05K3/02 ; H05K3/10
Abstract:
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
Public/Granted literature
- US20080261349A1 PROTECTIVE COATING FOR PLANARIZATION Public/Granted day:2008-10-23
Information query
