Invention Grant
US08012797B2 Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
有权
用于形成包括具有指定几何形状的导电凸块的开口的可堆叠半导体器件封装的方法
- Patent Title: Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
- Patent Title (中): 用于形成包括具有指定几何形状的导电凸块的开口的可堆叠半导体器件封装的方法
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Application No.: US12547063Application Date: 2009-08-25
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Publication No.: US08012797B2Publication Date: 2011-09-06
- Inventor: Chi-Chih Shen , Jen-Chuan Chen , Wen-Hsiung Chang , Chi-Chih Chu , Cheng-Yi Weng
- Applicant: Chi-Chih Shen , Jen-Chuan Chen , Wen-Hsiung Chang , Chi-Chih Chu , Cheng-Yi Weng
- Applicant Address: TW Kaosiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaosiung
- Agency: Cooley LLP
- Priority: TW98100325A 20090107
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50

Abstract:
In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.
Public/Granted literature
- US20100171207A1 STACKABLE SEMICONDUCTOR DEVICE PACKAGES Public/Granted day:2010-07-08
Information query
IPC分类: