Invention Grant
- Patent Title: Method of fabricating a stacked type chip package structure and a stacked type package structure
- Patent Title (中): 堆叠式芯片封装结构的制造方法和层叠型封装结构
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Application No.: US12428263Application Date: 2009-04-22
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Publication No.: US08012800B2Publication Date: 2011-09-06
- Inventor: Chau-Chin Yang
- Applicant: Chau-Chin Yang
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: J.C. Patents
- Priority: TW97119932A 20080529
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50
Abstract:
A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps.
Public/Granted literature
- US20090298227A1 METHOD OF FABRICATING A STACKED TYPE CHIP PACKAGE STRUCTURE AND A STACKED TYPE PACKAGE STRUCTURE Public/Granted day:2009-12-03
Information query
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