Invention Grant
- Patent Title: Method for fabricating isolated integrated semiconductor structures
- Patent Title (中): 隔离集成半导体结构的制造方法
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Application No.: US12137817Application Date: 2008-06-12
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Publication No.: US08012842B2Publication Date: 2011-09-06
- Inventor: Scott Balster , Badih El-Kareh , Hiroshi Yasuda
- Applicant: Scott Balster , Badih El-Kareh , Hiroshi Yasuda
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: DE102007056103 20071115
- Main IPC: H01L21/331
- IPC: H01L21/331

Abstract:
An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.
Public/Granted literature
- US20090127630A1 Method for Fabricating Isolated Integrated Semiconductor Structures Public/Granted day:2009-05-21
Information query
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