Invention Grant
- Patent Title: Manufacturing method for interconnection having stress-absorbing layer between the semiconductor substrate and the external connection terminal
- Patent Title (中): 用于在半导体衬底和外部连接端子之间具有应力吸收层的互连的制造方法
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Application No.: US12237750Application Date: 2008-09-25
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Publication No.: US08012864B2Publication Date: 2011-09-06
- Inventor: Haruki Ito , Nobuaki Hashimoto
- Applicant: Haruki Ito , Nobuaki Hashimoto
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2005-168373 20050608
- Main IPC: H01L21/28
- IPC: H01L21/28

Abstract:
A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.
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