Invention Grant
- Patent Title: Semiconductor test pad structures
- Patent Title (中): 半导体测试板结构
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Application No.: US12267021Application Date: 2008-11-07
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Publication No.: US08013333B2Publication Date: 2011-09-06
- Inventor: Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
- Applicant: Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Frank J. Spanitz
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
Public/Granted literature
- US20100117080A1 SEMICONDUCTOR TEST PAD STRUCTURES Public/Granted day:2010-05-13
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