Invention Grant
US08013376B2 Memory arrays, semiconductor constructions and electronic systems with transistor gates extending partially over SOI and unit cells within active region pedestals
有权
存储器阵列，半导体结构和电子系统，其中晶体管栅极部分地延伸在有源区域基座内的SOI和单元电池上
- Patent Title: Memory arrays, semiconductor constructions and electronic systems with transistor gates extending partially over SOI and unit cells within active region pedestals
- Patent Title (中): 存储器阵列，半导体结构和电子系统，其中晶体管栅极部分地延伸在有源区域基座内的SOI和单元电池上
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Application No.: US12852169Application Date: 2010-08-06
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Publication No.: US08013376B2Publication Date: 2011-09-06
- Inventor: Kunal R. Parekh
- Applicant: Kunal R. Parekh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/108
- IPC: H01L27/108
Abstract:
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
Public/Granted literature
- US20100295109A1 Memory Arrays, Semiconductor Constructions And Electronic Systems Public/Granted day:2010-11-25
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