A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.