Invention Grant
- Patent Title: Interconnect structure to reduce stress induced voiding effect
- Patent Title (中): 互连结构,减少应力引起的排尿效应
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Application No.: US12363565Application Date: 2009-01-30
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Publication No.: US08013451B2Publication Date: 2011-09-06
- Inventor: Chien-Jung Wang
- Applicant: Chien-Jung Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/49
- IPC: H01L23/49

Abstract:
An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
Public/Granted literature
- US20090134526A1 Interconnect Structure to Reduce Stress Induced Voiding Effect Public/Granted day:2009-05-28
Information query
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