Invention Grant
- Patent Title: Reference voltage circuit
- Patent Title (中): 参考电压电路
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Application No.: US12641090Application Date: 2009-12-17
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Publication No.: US08013588B2Publication Date: 2011-09-06
- Inventor: Takashi Imura
- Applicant: Takashi Imura
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2008-327935 20081224
- Main IPC: G05F1/445
- IPC: G05F1/445 ; G05F1/56

Abstract:
Provided is a reference voltage circuit capable of generating a temperature-independent reference voltage more stably. Each of N-type metal oxide semiconductor (NMOS) transistors (1) and (2) has a source and a back gate that are short-circuited, and hence threshold voltages (Vth1) and (Vth2) of the NMOS transistors (1) and (2) respectively depend only on process fluctuations in the NMOS transistors (1) and (2) and not on process fluctuations in other elements. As a result, a temperature-independent reference voltage (Vref) may be generated more stably.
Public/Granted literature
- US20100156386A1 REFERENCE VOLTAGE CIRCUIT Public/Granted day:2010-06-24
Information query
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