Invention Grant
- Patent Title: Multi-mode circuit and a method for preventing degradation in the multi-mode circuit
- Patent Title (中): 多模式电路以及用于防止多模电路劣化的方法
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Application No.: US12703793Application Date: 2010-02-11
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Publication No.: US08013635B2Publication Date: 2011-09-06
- Inventor: Palkesh Jain , Nagaraj Savithri , Usha Narasimha
- Applicant: Palkesh Jain , Nagaraj Savithri , Usha Narasimha
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.
Public/Granted literature
- US20110193588A1 MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT Public/Granted day:2011-08-11
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