There is provided a clock signal selection circuit including: a first AND circuit (AND_A1) outputting a logical product signal of a clock selection signal and a first control signal; a second AND circuit (AND_A2) outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal; a first flip-flop (FF_A2) inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal; and a second flip-flop (FF_B2) inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal, and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal.