Invention Grant
- Patent Title: Semiconductor integrated circuit
- Patent Title (中): 半导体集成电路
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Application No.: US12268709Application Date: 2008-11-11
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Publication No.: US08014114B2Publication Date: 2011-09-06
- Inventor: Tetsuo Shimamura
- Applicant: Tetsuo Shimamura
- Applicant Address: JP Moriguchi-shi JP Ora-gun
- Assignee: SANYO Electric Co., Ltd.,SANYO Semiconductor Co., Ltd.
- Current Assignee: SANYO Electric Co., Ltd.,SANYO Semiconductor Co., Ltd.
- Current Assignee Address: JP Moriguchi-shi JP Ora-gun
- Agency: Morrison & Foerster LLP
- Priority: JP2007-296256 20071115
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H1/00 ; H02H1/04 ; H02H3/22

Abstract:
The invention provides a semiconductor integrated circuit preventing an electrostatic breakdown due to a surge voltage applied to a power supply wiring or a ground wiring and preventing noise interference between a digital circuit and an analog circuit. By providing a first electrostatic breakdown protection diode and a first electrostatic breakdown protection bipolar transistor in a first island region, the first electrostatic breakdown protection diode and the first electrostatic breakdown protection bipolar transistor turn on when a surge voltage is applied to a first ground wiring and protect a digital circuit against an electrostatic breakdown. Furthermore, a first isolation layer is contacted with the first ground wiring in a position that is more adjacent to a first ground pad than the digital circuit, and a second isolation layer is contacted with a second ground wiring in a position that is more adjacent to a second ground pad than an analog circuit. This prevents noise interference between the digital circuit and the analog circuit.
Public/Granted literature
- US20090128971A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2009-05-21
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