A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.