Invention Grant
- Patent Title: Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture
- Patent Title (中): 在多层全图互连架构的超节点中提供完全无阻塞的交换机
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Application No.: US11845211Application Date: 2007-08-27
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Publication No.: US08014387B2Publication Date: 2011-09-06
- Inventor: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
- Applicant: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Francis Lammes; Stephen J. Walder, Jr.; Diana R. Gerhardt
- Main IPC: H04L12/66
- IPC: H04L12/66

Abstract:
A mechanism is provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.
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