Invention Grant
US08014387B2 Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture 失效
在多层全图互连架构的超节点中提供完全无阻塞的交换机

Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture
Abstract:
A mechanism is provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.
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