Invention Grant
US08014422B2 Method and system for utilizing a single PLL to clock an array of DDFS for multi-protocol applications
有权
利用单个PLL为多协议应用的DDFS阵列提供时钟的方法和系统
- Patent Title: Method and system for utilizing a single PLL to clock an array of DDFS for multi-protocol applications
- Patent Title (中): 利用单个PLL为多协议应用的DDFS阵列提供时钟的方法和系统
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Application No.: US11864842Application Date: 2007-09-28
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Publication No.: US08014422B2Publication Date: 2011-09-06
- Inventor: Ahmadreza Rofougaran
- Applicant: Ahmadreza Rofougaran
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: McAndrews, Held & Malloy, Ltd.
- Main IPC: H04J1/00
- IPC: H04J1/00

Abstract:
Methods and systems for utilizing a single PLL to clock an array of DDFS for multi-protocol applications are disclosed. Aspects of one method may include generating a first signal for use in generating a plurality of local oscillator (LO) signals. The first signal may be communicated to a plurality of LO generators. Each of the LO signals may be generated independently of each other by a corresponding one of the LO generators. Each of the LO signals may be communicated to one or more mixers, where each mixer may perform down-conversion or up-conversion. A LO generator may utilize, for example, a DDFS or a digital delay circuit. A frequency of a LO signal may be varied by adjusting a divide factor for a divider that generates a reference clock for the DDFS or for a divider that generates a second signal used for mixing with a signal generated by the DDFS. The LO signal frequency may also be varied by adjusting frequency control words received by a DDFS.
Public/Granted literature
- US20090086738A1 Method And System For Utilizing A Single PLL To Clock An Array Of DDFS For Multi-Protocol Applications Public/Granted day:2009-04-02
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