Invention Grant
- Patent Title: Distributed micro instruction set processor architecture for high-efficiency signal processing
- Patent Title (中): 分布式微指令集处理器架构,用于高效率信号处理
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Application No.: US11841604Application Date: 2007-08-20
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Publication No.: US08014786B2Publication Date: 2011-09-06
- Inventor: Song Chen , Paul L. Chou , Christopher C. Woodthorpe , Venugopal Balasubramonian , Keith Rieken
- Applicant: Song Chen , Paul L. Chou , Christopher C. Woodthorpe , Venugopal Balasubramonian , Keith Rieken
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Dickstein Shapiro LLP
- Main IPC: H04Q7/20
- IPC: H04Q7/20

Abstract:
A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.
Public/Granted literature
- US20080084850A1 DISTRIBUTED MICRO INSTRUCTION SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING Public/Granted day:2008-04-10
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