Invention Grant
- Patent Title: Data processing apparatus and method for performing floating point multiplication
- Patent Title (中): 用于执行浮点乘法的数据处理装置和方法
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Application No.: US10999154Application Date: 2004-11-30
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Publication No.: US08015231B2Publication Date: 2011-09-06
- Inventor: David Raymond Lutz , Christopher Neal Hinds
- Applicant: David Raymond Lutz , Christopher Neal Hinds
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F7/52
- IPC: G06F7/52

Abstract:
A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation with a first rounded result and a second adder logic performs a second sum operation with a second rounded result. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.
Public/Granted literature
- US20060117080A1 Data processing apparatus and method for performing floating point multiplication Public/Granted day:2006-06-01
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