Invention Grant
US08015366B2 Accessing memory and processor caches of nodes in multi-node configurations
有权
访问多节点配置中节点的内存和处理器缓存
- Patent Title: Accessing memory and processor caches of nodes in multi-node configurations
- Patent Title (中): 访问多节点配置中节点的内存和处理器缓存
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Application No.: US12179386Application Date: 2008-07-24
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Publication No.: US08015366B2Publication Date: 2011-09-06
- Inventor: James C. Wilson , Wolf-Dietrich Weber
- Applicant: James C. Wilson , Wolf-Dietrich Weber
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fenwick & West LLP
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a processor in a first node and passes the request for data to other nodes through an expansion port (or scalability port). The method also starts an access of a memory in response to the request for data and snoops a processor cache of each processor in each node. The method accordingly identifies the location of the data in either the processor cache or memory in the node having the processor issuing the request or in a processor cache or memory of another node.
Public/Granted literature
- US20090024688A1 Accessing Memory And Processor Caches Of Nodes In Multi-Node Configurations Public/Granted day:2009-01-22
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