Invention Grant
US08015392B2 Updating instructions to free core in multi-core processor with core sequence table indicating linking of thread sequences for processing queued packets 有权
更新指令,以核心顺序表表示多核处理器中的核心,指示用于处理排队数据包的线程序列的链接

Updating instructions to free core in multi-core processor with core sequence table indicating linking of thread sequences for processing queued packets
Abstract:
A method of updating execution instructions of a multi-core processor comprising receiving execution instructions at a processor including multiple programmable processing cores integrated on a single die, selecting subset of at least one of the cores, and loading at least a portion of the execution instructions to the subset of cores and replacing existing execution instructions, associated with the first subset of programmable processing cores, with the received execution instructions while at least one of the other cores continues to process received packets, wherein a sequence of threads provided by the cores sequentially retrieve packets to process from at least one queue, the sequence proceeding from a subsequence of at least one thread of one core to a subsequence of at least one thread on another core and wherein the sequence of threads is specified by data identifying, at least, the next core in the sequence.
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