Invention Grant
US08015425B1 Power reduction techniques for components in integrated circuits 有权
降低集成电路元件的技术

Power reduction techniques for components in integrated circuits
Abstract:
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.
Information query
Patent Agency Ranking
0/0