Invention Grant
- Patent Title: Power reduction techniques for components in integrated circuits
- Patent Title (中): 降低集成电路元件的技术
-
Application No.: US12536298Application Date: 2009-08-05
-
Publication No.: US08015425B1Publication Date: 2011-09-06
- Inventor: Aaron Charles Egier , David Neto
- Applicant: Aaron Charles Egier , David Neto
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/32 ; G06F17/50

Abstract:
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.
Information query