A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.