Invention Grant
- Patent Title: Processor debugging apparatus and processor debugging method
- Patent Title (中): 处理器调试设备和处理器调试方法
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Application No.: US10986912Application Date: 2004-11-15
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Publication No.: US08015447B2Publication Date: 2011-09-06
- Inventor: Hideo Yamashita , Ryuji Kan
- Applicant: Hideo Yamashita , Ryuji Kan
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2004-222398 20040729
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
Public/Granted literature
- US20060026470A1 Processor debugging apparatus and processor debugging method Public/Granted day:2006-02-02
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