Invention Grant
- Patent Title: Test circuit
- Patent Title (中): 测试电路
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Application No.: US12149742Application Date: 2008-05-07
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Publication No.: US08015462B2Publication Date: 2011-09-06
- Inventor: Yoshiyuki Nakamura , Toshiharu Asaka , Toshiyuki Maeda , Tomonori Sasaki
- Applicant: Yoshiyuki Nakamura , Toshiharu Asaka , Toshiyuki Maeda , Tomonori Sasaki
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn Intellectual Property Law Group, PLLC
- Priority: JP2007-127173 20070511; JP2007-280745 20071029
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
Public/Granted literature
- US20080281547A1 Test circuit Public/Granted day:2008-11-13
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