Invention Grant
US08015463B2 IC with TAP, DIO interface, SIPE, and PISO circuits 有权
IC与TAP,DIO接口,SIPE和PISO电路

IC with TAP, DIO interface, SIPE, and PISO circuits
Abstract:
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
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