Invention Grant
- Patent Title: Segmented scan paths with cache bit memory inputs
- Patent Title (中): 具有缓存位存储器输入的分段扫描路径
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Application No.: US12204267Application Date: 2008-09-04
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Publication No.: US08015464B2Publication Date: 2011-09-06
- Inventor: Lee D. Whetsel , Joel J. Graber
- Applicant: Lee D. Whetsel , Joel J. Graber
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
Public/Granted literature
- US20080320351A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS Public/Granted day:2008-12-25
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