A system and method for transforming a physical representation of a functional logic system or sub-system to a logical representation of the same functional logic system or sub-system. One embodiment provides a method comprising loading a physical hardware description language (HDL) representation of the system or creating a physical HDL representation from a physical schematic of the system, identifying the power nets and component blocks, identifying initial conditions on the power nets and component blocks, converting connector blocks to hierarchical IO logical HDL representations, converting appropriate component blocks to logical HDL representations, deleting component blocks appropriate for deletion, and converting resistor components to logical HDL representations.