One embodiment of the present invention provides a system that performs sequential equivalence checking between integrated circuit (IC) designs. During operation, the system receives a first IC design and a second IC design. Each of the first and second IC designs includes a top design level and a bottom design level, and the bottom design levels include one or more sub-blocks within the corresponding top design levels. The system then verifies if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the second design. Note that two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs. The system additionally verifies if the top design level of the first design is conditionally equivalent to the top design level of the second design and if the first design is temporally equivalent to the second design.