Invention Grant
- Patent Title: Method and system for reducing inter-layer capacitance in integrated circuits
- Patent Title (中): 集成电路中降低层间电容的方法和系统
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Application No.: US12156281Application Date: 2008-05-30
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Publication No.: US08015540B2Publication Date: 2011-09-06
- Inventor: Kunal N. Taravade , Neal Callan , Paul G. Filseth
- Applicant: Kunal N. Taravade , Neal Callan , Paul G. Filseth
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
Public/Granted literature
- US20080235643A1 Method and system for reducing inter-layer capacitance in integrated circuits Public/Granted day:2008-09-25
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