Invention Grant
- Patent Title: Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路装置及半导体集成电路装置的制造方法
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Application No.: US12558498Application Date: 2009-09-12
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Publication No.: US08017464B2Publication Date: 2011-09-13
- Inventor: Masao Sugiyama , Yoshiyuki Kaneko , Yoshinori Kondo , Masayoshi Hirasawa
- Applicant: Masao Sugiyama , Yoshiyuki Kaneko , Yoshinori Kondo , Masayoshi Hirasawa
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2008-249416 20080929
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234

Abstract:
As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects.In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.
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