Invention Grant
- Patent Title: Semiconductor package having through-hole vias on saw streets formed with partial saw
- Patent Title (中): 具有通道孔的半导体封装形成有部分锯
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Application No.: US12533160Application Date: 2009-07-31
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Publication No.: US08017501B2Publication Date: 2011-09-13
- Inventor: Byung Tai Do , Heap Hoe Kuan , Linda Pei Ee Chua
- Applicant: Byung Tai Do , Heap Hoe Kuan , Linda Pei Ee Chua
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group
- Agent Robert D. Atkins
- Main IPC: H01L21/98
- IPC: H01L21/98 ; H01L21/78

Abstract:
A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The semiconductor wafer has a saw street between each die. A trench is cut in the saw street without using support material to support the wafer. The trench extends only partially through the wafer. The uncut portion of the saw street below the trench along a backside of the wafer providing structural support for the wafer without support material during formation a plurality of conductive vias in the saw streets adjacent to the contact pads, and electrical connection of the conductive vias to the contact pads. The uncut portion of the saw street below the trench along the backside of the wafer portion is removed. The semiconductor wafer is singulated along the saw street to separate the die.
Public/Granted literature
- US20090291526A1 Semiconductor Package Having Through-Hole Vias on Saw Streets Formed with Partial Saw Public/Granted day:2009-11-26
Information query
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