Invention Grant
- Patent Title: Method of manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12045438Application Date: 2008-03-10
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Publication No.: US08017511B2Publication Date: 2011-09-13
- Inventor: Hidetoshi Nakata
- Applicant: Hidetoshi Nakata
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2005-057330 20050302
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.
Public/Granted literature
- US20080160758A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2008-07-03
Information query
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