Invention Grant
- Patent Title: Semiconductor package having side walls and method for manufacturing the same
- Patent Title (中): 具有侧壁的半导体封装及其制造方法
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Application No.: US12261112Application Date: 2008-10-30
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Publication No.: US08018043B2Publication Date: 2011-09-13
- Inventor: Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Jong Hoon Kim
- Applicant: Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Jong Hoon Kim
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2008-0021983 20080310; KR10-2008-0085386 20080829
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.
Public/Granted literature
- US20090224392A1 SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2009-09-10
Information query
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