A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller for receiving an output signal of the (M−1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. Each divider divides the clock signal frequency inputted to the divider by ½. The output signal frequency of the power-down controller is obtained by dividing the frequency of the clock signal inputted to the first divider into ½M or ½(M-1) depending on the logic level of a control signal, which is indicative of the power down mode of the memory device.