An over-voltage tolerant input circuit has a pad. An Nwell bias circuit is electrically coupled to the pad. A current block circuit is electrically coupled to the Nwell bias circuit. The current block circuit has a control signal coupled to a gate of a transistor in a current path of the Nwell bias circuit. The current block circuit includes a logic gate having a first input coupled to the pad and a second input coupled to an over voltage signal of the Nwell bias circuit. An output of the logic gate is the control signal. An n-type transistor is coupled between the over voltage signal and the first input of the logic gate. A transistor has a gate electrically coupled to the control signal and has a drain coupled to the first input of the logic gate.