Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US12474498Application Date: 2009-05-29
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Publication No.: US08018756B2Publication Date: 2011-09-13
- Inventor: Osamu Hirabayashi
- Applicant: Osamu Hirabayashi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-147572 20080605
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C5/06 ; G11C7/00

Abstract:
A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell.
Public/Granted literature
- US20090303777A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2009-12-10
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