Invention Grant
US08019946B2 Method and system for securing instruction caches using cache line locking 失效
使用高速缓存行锁定来保护指令高速缓存的方法和系统

Method and system for securing instruction caches using cache line locking
Abstract:
A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves providing security critical instructions to indicate a security critical code section; and implementing an I-cache locking policy to prevent unauthorized eviction and replacement of security critical instructions in the I-cache. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.
Information query
Patent Agency Ranking
0/0