Invention Grant
US08019946B2 Method and system for securing instruction caches using cache line locking
失效
使用高速缓存行锁定来保护指令高速缓存的方法和系统
- Patent Title: Method and system for securing instruction caches using cache line locking
- Patent Title (中): 使用高速缓存行锁定来保护指令高速缓存的方法和系统
-
Application No.: US12183908Application Date: 2008-07-31
-
Publication No.: US08019946B2Publication Date: 2011-09-13
- Inventor: Onur Aciicmez , Jean-Pierre Seifert , Qingwei Ma , Xinwen Zhang
- Applicant: Onur Aciicmez , Jean-Pierre Seifert , Qingwei Ma , Xinwen Zhang
- Applicant Address: KR Suwon
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon
- Agency: Beyer Law Group LLP
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A method and system is provided for securing micro-architectural instruction caches (I-caches). Securing an I-cache involves providing security critical instructions to indicate a security critical code section; and implementing an I-cache locking policy to prevent unauthorized eviction and replacement of security critical instructions in the I-cache. Securing the I-cache may further involve dynamically partitioning the I-cache into multiple logical partitions, and sharing access to the I-cache by an I-cache mapping policy that provides access to each I-cache partition by only one logical processor.
Public/Granted literature
- US20100030964A1 METHOD AND SYSTEM FOR SECURING INSTRUCTION CACHES USING CACHE LINE LOCKING Public/Granted day:2010-02-04
Information query