There is provided a parity check encoder (100) comprising a data memory (PPDM) configured for storing input data, a calculation/parity result data store (CPRDS), and a selector/serializer (SS). The CPRDS (104,106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SS (108) is coupled to the PPDM and CPRDS. The SS is configured to generate an encoded output sequence using the input data and parity bits. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix. A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).