Invention Grant
- Patent Title: Die stacking structure and fabricating method thereof
- Patent Title (中): 芯片堆叠结构及其制造方法
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Application No.: US12484250Application Date: 2009-06-15
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Publication No.: US08026585B2Publication Date: 2011-09-27
- Inventor: Yung-Fa Chou , Ding-Ming Kwai
- Applicant: Yung-Fa Chou , Ding-Ming Kwai
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW98110661A 20090331
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.
Public/Granted literature
- US20100244220A1 LAYOUT STRUCTURE AND METHOD OF DIE Public/Granted day:2010-09-30
Information query
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