Invention Grant
- Patent Title: IC package reducing wiring layers on substrate and its carrier
- Patent Title (中): IC封装减少了衬底及其载体上的布线层
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Application No.: US12825811Application Date: 2010-06-29
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Publication No.: US08026615B2Publication Date: 2011-09-27
- Inventor: Hung Tsun Lin , Wu Chang Tu , Cheng Ting Wu
- Applicant: Hung Tsun Lin , Wu Chang Tu , Cheng Ting Wu
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technologies Inc.
- Current Assignee: Chipmos Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King
- Priority: TW96102754A 20070124
- Main IPC: H01L23/49
- IPC: H01L23/49 ; H05K1/11

Abstract:
An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.
Public/Granted literature
- US20100264540A1 IC Package Reducing Wiring Layers on Substrate and Its Carrier Public/Granted day:2010-10-21
Information query
IPC分类: