A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.