A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flop of a next stage. A second D-type flip-flop receives one bit of enable control signal, and the output of each of the second D-type flip-flops connects to the input of a second D-type flip-flop of a next stage. A multiplexer contains two input terminals and an enable control signal receiving terminal, wherein one input terminal is used to receive the input data received by the first D-type flip-flop, and the enable control signal receiving terminal receives the enable control signal received by the second D-type flip-flop. A D-type latch outputs the data, and the output data is fed back to another input terminal of the multiplexer so as to be selected as a data output when a next set of data are input.